1. Field of the Invention
The present invention relates to a semiconductor memory device having a plurality of RAMs of differing memory spaces on the same substrate, for example, on the same silicon, and a method for testing the same, and more particularly to a circuit configuration that makes parallel testing possible.
2. Description of the Related Art
In recent system LSIs, a plurality of RAMs have come to be mounted on the same silicon according to the needs on the system side; for example, a plurality of RAMs differing in capacity and in bit width have been accommodated on a single chip. One of the major problems involved in the production of such a system LSI having a plurality of RAMs mounted thereon is that the time required to test the RAMs becomes long.
In particular, in the case of RAMs designed to such specifications that provide for a common test I/O bus, common address, and common control signal and that control access to each RAM by a chip select signal, the only test method usually available has been the serial test method that carries out a test on a RAM by RAM basis; in this case, the total test time increases as the number of RAMs mounted increases.
If the test time is to be reduced here, an environment where parallel testing can be performed using testers can be provided for RAMs having the same memory space by providing an I/O bus, address, and control signal special for each individual RAM. In this way, the test time can be reduced and the productivity can thus be increased.
However, for RAMs having different memory spaces, parallel testing of the RAMs cannot be done. The reason is that, in the method of using a memory tester commonly practiced today, X and Y addresses are assigned in the row and column directions of a memory in order to access the memory space, and a test pattern is generated. As a result, in the case of RAMs having different memory spaces, since the memory row/column organization differs between the different RAMs, the same X and Y addresses cannot be assigned, and therefore, the test cannot be performed using the same test pattern (for example, HALF-MARCH).
Accordingly, in the case where a plurality of RAMs are mounted and some of the RAMs have different memory spaces, the RAMs have to be divided into groups each consisting of RAMs having the same memory space, and parallel testing has to be done on a group by group basis; this has lead to the problem of increased test time.